AUTHORS: Larissa Soares, Cleonilson Souza

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ABSTRACT: Testing of integrated circuits (ICs) is always a challenge because the continuous miniaturization process and consequently increase of transistor density in microelectronic industry. Nowadays, the industry has to handle with defects that traditional testing approaches can not detect. The result of this imprecise testing process is the increase number of defective ICs that reach the end consumer. To improve the quality of IC testing, a new approach of fault modeling is being adopted which is not based on transistor or logic gate level, but in the IC layout perspective itself. This paper describes the meaning of testing based on layout perspective, particularly, Cell-Aware Testing (CAT) methodology, and a practical approach to obtain the matrix of defects, in which is the set of test patterns to each modelled fault coming from CAT, and that is the CAT’s main result. Experimental simulation results show the matrix of defects obtained for a specific standard cell that can be immediately used by an ATPG.

KEYWORDS: Defect, Fault-model, Layout-perspective, Defect insertion

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